As is known, nonvolatile phase-change memories, namely the so-called embedded phase-change memories (ePCMs), represent new-generation integrated memories, in which storage of information is obtained by exploiting phase-change materials, which have the property of being able to switch between phases that have resistivities of considerably different value. In particular, these materials may switch between an amorphous phase, with high resistivity, and a crystalline or polycrystalline phase, with low resistivity. Consequently, in a phase-change memory cell it is possible to associate a different value of a datum stored in the cell to a respective phase of a memory element of the cell. For example, it is possible to use elements of group VI of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), referred to as “chalcogenides” or “chalcogenic materials”, to form phase-change memory elements. In particular, an alloy made up of germanium (Ge), antimony (Sb) and tellurium (Te), known as GST (having chemical composition Ge2Sb2Te5) currently finds wide use in such memory elements.
Phase switching in a memory element may be obtained by locally increasing the temperature of the region of chalcogenic material, for example by causing passage of an electric programming current through resistive electrodes (generally known as “heaters”) arranged in contact with the region of chalcogenic material. The electric current, by the Joule effect, generates the temperature profile necessary for phase change. In particular, when the chalcogenic material is in the amorphous state, with high resistivity (the so-called RESET state), it is necessary to apply a first current pulse (the so-called SET pulse) of a duration and amplitude such as to enable the chalcogenic material to cool slowly. Subjected to this treatment, the chalcogenic material changes state and switches from the high-resistivity state to a low-resistivity crystalline state (the so-called SET state). Conversely, when the chalcogenic material is in the SET state, it is necessary to apply a second current pulse (the so-called RESET pulse) of large amplitude and short duration so as to cause the chalcogenic material to return into the high-resistivity amorphous state.
As is known, a number of memory cells may be arranged in a memory array in rows formed by wordlines (WL) and columns formed by bitlines (BL).
Selectors, for example MOSFETs or BJTs, are electrically connected to the heaters so as to enable selective passage of the electric programming current through a respective memory element of a specific memory cell. Undesired programming of non-selected memory cells is thus prevented.
Use of selectors of a BJT type affords advantages over the MOSFET technology, such as a considerable reduction of the area occupied by the cells. However, generally, the use of BJT selectors causes a higher power consumption and the need to use a higher supply voltage on account of the high threshold voltage of the BJT and of the current passing through the base terminal of the BJT.
In ePCM circuits of a known type, reading of the datum stored in a memory cell may be carried out by applying to the memory element of chalcogenic material a voltage sufficiently low as not to cause a sensible heating thereof, and then by reading the value of the current that flows in the memory cell. Given that the current is proportional to the conductivity of the chalcogenic material, it is possible to determine in which phase the material is, and thus arrive at the datum stored in the memory cell. Further known is an ePCM-reading architecture of a differential type, in which two memory cells of opposite state are associated to each bit. For example, a bit has a value “1” if a first memory cell and a second memory cell associated to the bit are, respectively, in the SET state and in the RESET state, and has a value “0” if the first and second memory cells are, respectively, in the RESET state and in the SET state.
Differential-reading architectures for ePCMs afford advantages in terms of reliability, in so far as the datum is stored in a redundant way and further does not require generation of a reference current in so far as reading is carried out simply by comparing the respective currents that flow in the cells associated to a same bit.
Comparison of the currents in memory cells of a differential type is carried out using a sense amplifier, which may be selectively connected to the bitline associated to the memory cells. In this case, also the sense amplifier has a differential structure, and it is necessary to minimize the offset between elements of the amplifier to improve the accuracy of the reading operation.
In general, in reading architectures for nonvolatile memories of a known type, it is necessary for the sense amplifier to be able to operate at a supply voltage higher than the biasing voltage of the bitlines. In the case of memories with selector of a BJT type, for example, a reading architecture of a known type would render necessary supply of the sense amplifiers at a voltage higher than 1.8 V (on account of process corners and temperature), whereas the supply voltage available on the device tends to be considerably lower, for example between 1 V and 1.3 V in 40-nm technological processes, and between 0.9 V and 1.1 V in 28-nm technological processes. For this reason, the sense amplifiers would have to be supplied at a boosted voltage using charge pumps, thus increasing power consumption thereof. For example, using a one-stage charge pump, power consumption of the sense amplifier is multiplied by a factor greater than 2.